In LLVM, a matcher table is a table generated by TableGen to direct the instruction selection process. The matcher table is actually a state machine. For each instruction selection algorithm on a each target, a matcher table (.inc C++ file) is generated by a corresponding TableGen backend (e.g. SelectionDAG has a TableGen backend DAGISel).
To dump all records in an architecture, run this in the llvm-project source directory:
llvm-tblgen -print-records -I llvm/lib/Target/X86 -I llvm/include -I llvm/lib/Target llvm/lib/Target/X86/X86.td -o x86-records.tdThe x86-records.td file contains all the information TableGen needs to produce a matcher table, including instructions, register info, ABI, etc. Each piece of information is stored in a concrete record.
A single instruction comes with its own pattern to match, but this is not the only pattern that can produce this instruction. Oftentimes there are anonymous concrete records (because we don’t care what they are called) with the class Pat/Pattern defined elsewhere to match other types of DAG nodes as this instruction.