📅 Wednesday, June 5th, 2024

Trust your hunches. They're usually based on facts filed away just below the conscious level.

— Joyce Brothers

ECS154A Lecture:

  • pipeline hazards
    • data hazard: value not written to register yet
    • control hazard: next instruction not decided yet due to branching
  • spatial locality with direct mapped cache
    • address format: tag - set - block offset - byte offset
    • Each set holds a single block containing a contigious chunk of memory to hold neighboring data of a memory read, and the block offset determines which word to read within the block
    • Spatial locality can help reduce compulsory misses for contigious reads, at the cost of larger blocks.
  • capacity miss: cache is too small and some blocks need to be evicted (e.g., via LRU eviction policy)
  • The TLB uses a fully associative cache (99% hit rates) which reduces memory access overhead from 2 cycles to 1 cycle.
  • Each process has its own page table. How do we handle switching processes for TLB?
    • Either: make PID part of the tag
    • Or: Flush TLB when context switching