2024-04-26

📅 Friday, April 26th, 2024

The secret of success is constancy to purpose.

— Benjamin Disraeli

• How a C++ compiler implements exception handling

ECS154A Lecture: 8-op ALU design

Design an ALU, given the following operations: add, sub, mul2 (multiply by 2), not, xor, and, or.

Notice how we can implement add & sub & mul2 together, and implement not & xor together, so only four mux inputs are needed

		$o{p}_{2:0}$	$xnot$	$s_{o{p}_{1:0}}$	$m_{sub}$	$m_{mul}$	$C_{in}$
0	add	000	x	00	0	x	0
1	sub	001	x	00	1	1	1
2	mul2	010	x	00	1	0	0
3	-	011	x	xx	x	x	x
4	not	100	1	11	x	x	x
5	xor	101	0	11	x	x	x
6	and	110	x	01	x	x	x
7	or	111	x	10	x	x	x

Note that for subtraction, we are taking the two’s complement of B, but we don’t add 1 to the ~B immediately; we add the one as a carry-in ($C_{in}$) in the full adder.

Now that we’re done with the actual calculation, we need to design the ALU controller.

ECS154A Discussion: 8-op ALU controller

K-map for $xnot$:

$o{p}_2$ \ $o{p}_{1:0}$	00	01	11	10
0	x	x	x	x
1	1	0	x	x

We can make a group of four (column 00 and column 10) thanks to the three don’t cares which we can pretend are just ones.

$$xnot=\overline{o{p}_0}$$

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K-map for $s_{o{p}_0}$

$o{p}_2$ \ $o{p}_{1:0}$	00	01	11	10
0	0	0	x	0
1	1	1	0	1
We can’t really simplify much here. We can go with a two-element group that wraps around (op = 100, 110), and then overlap that with another two-element group (op = 100, 101).

$$\begin{array}{rl}{s}_{o{p}_0}& =o{p}_2\overline{o{p}_1}+o{p}_2\overline{o{p}_0}\\ & =o{p}_2\left(\overline{o{p}_1}+\overline{o{p}_0}\right)\\ & =o{p}_2\overline{o{p}_{1}o{p}_0}\end{array}$$

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K-map for $s_{o{p}_1}$

$o{p}_2$ \ $o{p}_{1:0}$	00	01	11	10
0	0	0	x	0
1	1	1	1	0

$$s_{o{p}_1}=\overline{o{p}_1}o{p}_2+o{p}_{1}o{p}_0$$

---

K-map for $m_{sub}$

$o{p}_2$ \ $o{p}_{1:0}$	00	01	11	10
0	0	1	x	1
1	x	x	x	x

Using the don’t cares, we can form two four-element groups (columns 01 & 11, and columns 11 & 10).

$$m_{sub}=o{p}_0+o{p}_1$$

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K-map for $m_{mul}$

$o{p}_2$ \ $o{p}_{1:0}$	00	01	11	10
0	x	1	x	0
1	x	x	x	x

$$m_{mul}=o{p}_0$$

---

K-map for $C_{in}$

$o{p}_2$ \ $o{p}_{1:0}$	00	01	11	10
0	0	1	x	0
1	x	x	x	x

It turns out that:

$$C_{in}=m_{mul}$$

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We need to find a way to save the ALU flags and prevent some of them from changing when they are not supposed to (e.g., the carry flag shouldn’t be changed on any logic operation). In other words, we need to decide, using $op$, if we want to pass the new flags into the actual flag registers.

		$o{p}_{2:0}$	$V_P$	$C_P$	$N_P$	$Z_P$
0	add	000	1	1	1	1
1	sub	001	1	1	1	1
2	mul2	010	1	1	1	1
3	-	011	x	x	x	x
4	not	100	0	0	1	1
5	xor	101	0	0	1	1
6	and	110	0	0	1	1
7	or	111	0	0	1	1

Note that $V_P=C_P$ and $N_P=Z_P=1$. We can define $\overline{\mathrm{mask}}=V_P=C_P=\overline{o{p}_2}$. When $\mathrm{mask}=1$, we want to prevent V & C from being saved; otherwise, we want to pass them to the actual registers. For now, saving to registers won’t be shown here (registers are covered next week). I think we need a slightly different design of the circuit when actual registers are involved, e.g., for a D flip-flop, we can use a mux that takes in $F$ and $F^{\prime }$ as inputs and $\mathrm{mask}$ as the select bit.

Expect around 6 operations for an ALU design question on the exam.

SOC001 Discussion: no notes

• SOC001 2024-04-26 discussion

MGT011A Discussion: no notes